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New: A brand-new, unused, unopened, undamaged item in its original packaging (where packaging is applicable). Packaging should be the same as what is found in a retail store, unless the item is handmade or was packaged by the manufacturer in non-retail packaging, such as an unprinted box or plastic bag. See the seller's listing for full details. Type: bios EFI chip MPN: 820-2936-B Compatible Motherboard Brand: A1278 2011 820-2936-B Model: A1278 2011 820-2936-B Brand: A1278 2011 820-2936-B Country/Region of Manufacture: United States Compatible Socket Type: A1278 2011 820-2936-B UPC: Does not apply.

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Related parts for WG82578DM S LGY6 Part Number Description Manufacturer Datasheet Intel Corporation. Microprocessor: Intel Celeron M Processor 320 and Ultra Low Voltage Intel Celeron M Processor at 600MHz Intel Corporation.

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(786 pages) IC MPU INTEL486 RISC 32-BIT 0.8 MICRON 33MHZ 5V 196PQFP Intel Corporation. (38 pages) WG82578DM S LGY6 Summary of contents. Smart speed operation for automatic speed reduction on faulty cable plants — PMA loopback capable (no echo cancel) 1. Refer to the latest Intel® 82578 Specification Update for more details. The MAC is incorporated into the Intel June 2010 Advanced cable diagnostics . Intel Corporation (“Intel”).

In the event that you do not agree with any of these terms and conditions, do not use or install the Pre-Release Product and promptly return it unused to Intel. 6 2.4 Transitions between SMBus and PCIe interfaces.

8 2.4.1 Switching from SMBus to PCIe. 8 2.4.2 Switching from PCIe to SMBus. 8 2.5 Intel® 5 Series Express Chipset/82578 – SMBus/PCIe Interconnects. 9 3.0 Pin Interface.

11 3.1 Pin Assignment. 11 3.1.1 Signal Type Definitions. 11 3.1.2 PCIe Interface Pins (8).

Basic Configuration Software Words. 104 ® 9.4 Intel 5 Series Express Chipset/82578 NVM Contents. 106 ® 10.0 Intel 5 Series Express Chipset MAC Programming Interface. 107 10.1 Register Byte Ordering.

107 10.2 Register Conventions. 108 10.2.1 PCI Configuration and Status Registers - CSR Space.

Datasheet—82578 GbE PHY 11.4 I/O DC/AC Parameters. 165 11.4.1 3.3 Vdc DC/IO. 165 11.4.2 2.5 Vdc/IO. 166 11.4.3 Input Buffer Only.

167 11.4.4 SMBus AC I/O. 168 11.4.5 PCIe DC/AC Specifications. 168 11.5 Discrete/Integrated Magnetics Specifications. 171 11.6 Oscillator/Crystal Specifications. Removed old section 8. Updated section 10.3.1.11 (bit 12 and 13 desctiptions). Updated figure 1.

Updated table 2. Updated section 7.4 and 10.3.1.2 (added Intel® 5 Series Express Chipset references). Added power sequencing note to section 5.3.2. February 2010 2.2. Updated section 6.4.2.2 (added Windows. 7 reference). Updated Figure 1 (removed ferrite beads from diagram).

Updated Sections 1.2 (added note), 2.2 (added note), 2.3 (added note), and 7.2.2. April 2008 0.7 Added a discrete/integrated magnetics specifications table to Section 7.0. Mar 2008 0.6 Major revision (all sections). Jan 2008 0.5 Initial release (Intel Confidential). Overview The 82578 is a single port Gigabit Ethernet Physical Layer Transceiver (PHY). It connects to the Intel (MAC) through a dedicated interconnect. The 82578 supports operation at 1000/100/ 10 Mb/s data rates.

The PHY circuitry provides a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802. Introduction—82578 GbE PHY Crystal Testability Power Figure 1. 82578 Block Diagram 1.3 Main Flows The 82578 main interfaces are PCIe and SMBus on the host side and the MDI interface on the link side.

Transmit traffic is received from the MAC device through either PCIe or SMBus on the host interconnect and then transmitted on the MDI link. Intel Corporation ®. Intel 82578 Schematic and Layout Checklists, Intel Corporation ®. Intel 82578 MDI Differential Trace and Power Loss Calculators, Intel Corporation 1.5 Product Codes Table 1 lists the product ordering codes for the 82578 GbE controller. Refer to the ®. Introduction—82578 GbE PHY 1.6 Product Matrix Method of enabling/disabling features in SKUs Link Speed Platform Desktop Gigabit Desktop Performance Segment Description Device ID 82578 for Corporate 10EF Corporate 82578 for X Consumer 10F0 Consumer Extended. PCIe Interface Signals The signals used to connect between the MAC and the PHY in this mode are:.

Serial differential pair running at 1.25 Gb/s for Rx. Serial differential pair running at 1.25 Gb/s for Tx. 100 MHz differential clock input to the PHY running at 100 MHz.

No other device (like an external BMC) can be connected to SMLink0 when the 82578 is connected to the Intel 2.3.1 Overview SMBus is used as an interface to pass traffic between the 82578 and the Intel Express Chipset when the system low power state (Sx state). The interface is also used to enable the Intel as passing in-band information between them. ACKs, NACKs, STARTs, or STOPs) in the SMBus transaction. The polynomial for this CRC-8 is The PEC calculation is reset when any of the following occurs:. A STOP condition is detected on the host SMBus. An SMBus hang is detected on the host SMBus. The SMBCLK is detected high for 50 µs 7 82578 GbE PHY—Interconnects.

PERSTN signal is high. Switching the communication to SMBus is only needed to enable host wake up in low power states and is controlled by the Intel® 5 Series Express Chipset. The switching from PCIe to SMBus is done when the PERSTN signal is low.

Intel® 5 Series Express Chipset/82578 – SMBus/PCIe Interconnects The 82578 can be connected to any x1 PCIe port in Intel The PCIe port that connects to the 82578 is selected by PCHSTRP9, bits 11:8 in the SPI Flash descriptor region. For more information on this setting, please refer to the ®. Interconnects—82578 GbE PHY Note: This page intentionally left blank. The 82578 is packaged in a 48-pin package with a 0.4 mm lead pitch. There are 48 pins on the periphery and a die pad (Exposed Pad.) for ground.

Note: Refer to the reference schematics for pin connection details. Contact your Intel representative for access.

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3.1.1 Signal Type Definitions. Pin Interface—82578 GbE PHY 3.1.2 PCIe Interface Pins (8) Pin Name Pin # PERSTN 36 PETp 38 PETn 39 PERp 41 PERn 42 PECLKP 44 PECLKN 45 CLKREQN 48 3.1.3 SMBus Interface Pins (2) Pin Name Pin # SMBCLK 28 SMBDATA 31 1. AUX power means the power rail is available in all power states including transitions and Sx states with Wake on LAN (WoL) enabled.

PHY Pins (14) 3.1.5.1 LEDs (3) This table lists the functionality of the LED output pins. Refer to the Intel Family Platform Design Guide (PDG) for LED connection details.

Pin Name Pin # LED0 26 LED1 27 LED2 25 3.1.5.2 Analog Pins (11) Pin Name Pin# MDIPLUS0 13 MDIMINUS0 14 MDIPLUS1. Pin Interface—82578 GbE PHY 3.1.6 Testability Pins (5) Pin Name Pin # JTAGTCK 35 JTAGTDI 32 JTAGTDO 34 JTAGTMS 33 TESTEN 30 Note: The 82578 uses the JTAG interface to support XOR files for manufacturing test. BSDL is not supported.

3.1.7 Power Pins (13) Pin Name Pin # 8, 11, 16, 22, AVDD1P2. Package Type and Mechanical The 82578 mm, 48-pin QFN Halogen Free, Pb Free package with a pad size of 3. Package Dimensions 15 82578 GbE PHY—Package Notes: Controlling Dimension - Millimeter Reference Document - JEDEC MO-220 Tolerance Requirement for D1/E1: +/- 0.1 mm 3.80 3.95 0.144 0.150 3. Package—82578 GbE PHY 4.2 Package Electrical and Thermal Characteristics The thermal resistance from junction to case, qJC, is 15.1 ×C/Watt. The thermal resistance from junction to ambient, qJA follows: 4-layer PCB, 85 degrees ambient. Air Flow (m/s) No heat sink is required.

Maximum 119 1 118 2 116 qJA (×. C7 10 CTRL1p2 7 9 1.2V 37,46,47 1. 1.2V 8,11,8 GbE PHY—Package Magnetic Center Tap 1uf 1uf +3.3V LAN C6 C5 +3.3V LAN BCP69 R3 1.

1.2v. C1, C2,C5 – X5R 10 uF 6.3V. C8, C9 – X5R 4.7uF 6.3V. Package—82578 GbE PHY 4.4 Pinouts (Top View, Pins Down) RSVDVCC3P3 RSVDVCC3P3 LANDISABLEN VDD2P5OUT VDD3P3IN CTRL1P2 AVDD1P2 XTALOUT XTALIN AVDD1P2 Figure 5. 82578 Pinouts Pin 82578 5 48 Pin QFN 6 VCT 0.4 mm pin pitch with Exposed Pad RBIAS Pin 49 - VSSEPAD PERSTN 35 JTAGTCK 34 JTAGTDO. MDIPLUS2 9 MDIMINUS2 10 AVDD1P2 11 MDIPLUS3 12 MDIMINUS3 25 DVDD1P2 26 PETp 27 PETn 28 AVDD1P2 29 PERp 30 PERn 31 AVDD1P2 32 PECLKP 33 PECLKN 34 DVDD1P2 35 DVDD1P2 36 CLKREQN 49 82578 GbE PHY—Package Side Pin Number Bottom 13 Bottom 14 Bottom 15 Bottom 16 Bottom 17 Bottom 18 Bottom 19 Bottom 20 Bottom 21 Bottom 22 Bottom 23 Bottom 24 Top 37 Top 38 Top 39 Top 40 Top. Package—82578 GbE PHY Note: This page intentionally left blank.

Start PCIe training Send link status message PHY starts link auto-negotiation 82578 GbE PHY—Initialization Internal Xosc stabilizes Internal power on reset is de-asserted ® Wait for Intel 5 Series Express Chipset SMBus address valid MDIO registers are initialized by the MAC PHY establishes link. Platform power ramps up (3.3 V dc/2.5/1.2 Vdc) 2 XTAL is stable after T 3 Internal Power On Reset triggers T 4 PCIe training if PE reset is de-asserted. 5 Wait for Intel 6 Send Link Status message. 7 MAC configures the 82578. 8 PHY goes through auto-negotiation to acquire link. XTAL after XTAL is stable. Strapping options are latched.

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Asserting a 3.3 Vdc power on reset should move the PHY out of power down mode. PHY registers (page 0 in MDIO space and any aliases to page 0) are reset during a PHY soft reset. The rest of the 82578’s MDIO space is not reset. Timing Guarantees The 82578 guarantees the following start-up and power state transition related timing parameters.